TI公司的DRV835x系列是用于三相馬達(dá)的9-100V三相智能柵極驅(qū)動(dòng)器，集成了用于高邊和低邊的三個(gè)獨(dú)立半橋柵極驅(qū)動(dòng)器，電荷泵和線性穩(wěn)壓器，以及可選擇的三個(gè)電流分流放大器和350mA降壓穩(wěn)壓器，工作電壓6-95V，輸出電流2.5V-75V/350mA.主要用在3相無(wú)刷DC（BLDC）馬達(dá)模塊，風(fēng)扇，鼓風(fēng)機(jī)和泵，電動(dòng)自行車，電動(dòng)滑板車和電動(dòng)汽車，無(wú)人機(jī)，機(jī)器人遙控玩具，工廠自動(dòng)化和紡織機(jī)械。本文介紹了DRV835x系列主要特性和框圖，柵極驅(qū)動(dòng)器框圖，應(yīng)用電路以及評(píng)估板DRV8353RS-EVM主要特性和電路圖，材料清單與PCB設(shè)計(jì)圖。

The DRV835x family of devices are integrated 100-V gate drivers for three-phase motor drive applications.

These devices decrease system component count， cost， and complexity by integrating three independent halfbridgegate drivers， charge pump and linear regulator for the high-side and low-side gate driver supply voltages，optional triple current shunt amplifiers， and an optional 350-mA buck regulator. A standard serial peripheralinterface （SPI） provides a simple method for configuring the various device settings and reading fault diagnosticinformation through an external controller. Alternatively， a hardware interface （H/W） option allows for configuringthe most commonly used settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-Asource， 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage isgenerated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The lowsidegate drive supply voltage is generated using a linear regulator from the VM power supply that regulates theVGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver outputs. Asmart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current strengthallowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal ofexternal gate drive resistors and diodes reducing BOM component count， cost， and PCB area. The architecturealso uses an internal state machine to protect against gate-drive short-circuit events， control the half-bridge deadtime， and protect against dV/dt parasitic turnon of the external power MOSFET.

The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture， VMcan be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture，VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the deviceefficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrentmonitor reference.

The DRV8353 and DRV8353R devices integrate three， bidirectional current-shunt amplifiers for monitoring thecurrent level through each of the external half-bridges using a low-side shunt resistor. The gain setting of theshunt amplifier can be adjusted through the SPI or hardware interface with the SPI providing additional flexibilityto adjust the output bias point.

The DRV8350R and DRV8353R devices integrate a 350-mA buck regulator that can be used to power anexternal controller or other logic circuits. The buck regulator is implemented as a separate internal die that canuse either the same or a different power supply from the gate driver.

In addition to the high level of device integration， the DRV835x family of devices provides a wide range ofintegrated protection features. These features include power-supply undervoltage lockout （UVLO）， gate driveundervoltage lockout （GDUV）， VDS overcurrent monitoring （OCP）， gate-driver short-circuit detection （GDF）， andovertemperature shutdown （OTW/OTSD）。 Fault events are indicated by the nFAULT pin with detailed informationavailable in the SPI registers on the SPI device version.

The DRV835x family of devices are available in 0.5-mm pin pitch， QFN surface-mount packages. The QFN sizesare 5 × 5 mm for the 32-pin package， 6 × 6 mm for the 40-pin package， and 7 × 7 mm for the 48-pin package.

DRV8353RS主要特性：

1? 9 to 100-V， Triple Half-Bridge Gate Driver

– Optional Integrated Buck Regulator

– Optional Triple Low-Side Current ShuntAmplifiers

? Smart Gate Drive Architecture

– Adjustable Slew Rate Control For EMIPerformance

– VGS Handshake and Minimum Dead-TimeInsertion to Prevent Shoot-Through

– 50-mA to 1-A Peak Source Current

– 100-mA to 2-A Peak Sink Current

– dV/dt Mitigation Through Strong Pulldown

? Integrated Gate Driver Power Supplies

– High-Side Doubler Charge Pump For 100%PWM Duty Cycle Control

– Low-Side Linear Regulator

? Integrated LM5008A Buck Regulator

– 6 to 95-V Operating Voltage Range

– 2.5 to 75-V， 350-mA Output Capability

? Integrated Triple Current Shunt Amplifiers

– Adjustable Gain （5， 10， 20， 40 V/V）

– Bidirectional or Unidirectional Support

? 6x， 3x， 1x， and Independent PWM Modes

– Supports 120° Sensored Operation

? SPI or Hardware Interface Available

? Low-Power Sleep Mode （20 μA at VVM = 48-V）

? Integrated Protection Features

– VM Undervoltage Lockout （UVLO）

– Gate Drive Supply Undervoltage （GDUV）

– MOSFET VDS Overcurrent Protection （OCP）

– MOSFET Shoot-Through Prevention

– Gate Driver Fault （GDF）

– Thermal Warning and Shutdown （OTW/OTSD）

– Fault Condition Indicator （nFAULT）

DRV8353RS應(yīng)用：

? 3-Phase Brushless-DC （BLDC） Motor Modules

? Fans， Blowers， and Pumps

? E-Bikes， E-Scooters， and E-Mobility

? Power and Garden Tools， Lawn Mowers

? Drones， Robotics， and RC Toys

? Factory Automation and Textile Machines

圖1.DRV8350H框圖

圖2.DRV8350S框圖

圖3.DRV8350RH框圖

圖4.DRV8350RS框圖

圖5.DRV8353H框圖

圖6.DRV8353S框圖

圖7.DRV8353RH框圖

圖8.DRV8353RS框圖

圖9.柵極驅(qū)動(dòng)器框圖

圖10.DRV8353系列基本應(yīng)用電路圖（1）

圖11.DRV8353系列基本應(yīng)用電路圖（2）

評(píng)估板DRV8353RS-EVM

The DRV8353RS-EVM is a 15A， 3-phase brushless DC drive stage based on the DRV8353RS gate driver and CSD19532Q5B NexFET? MOSFETs.

The module has individual DC bus and phase voltage sense as well as individual low-side current shunt amplifiers， making this evaluation module ideal for sensorless BLDC algorithms. The module supplies MCU 3.3V power with an integrated 0.35A step down buck regulator. The drive stage has IDRIVE configuration， along with a fault pin and protection for short circuit， thermal， shoot-through， and under voltage conditions through configurable SPI.

評(píng)估板DRV8353RS-EVM主要特性：

9- to 95-V operation

15 A continuous/20 A peak H-bridge output current

Internal buck regulator

Three individual， internal low-side current shunt amplifiers

INSTASPIN FOC BLDC firmware available

圖12.評(píng)估板DRV8353RS-EVM外形圖

圖13.評(píng)估板DRV8353RS-EVM框圖

圖14.評(píng)估板DRV8353RS-EVM硬件連接圖（1）

圖15.評(píng)估板DRV8353RS-EVM硬件連接圖（2）

圖16.評(píng)估板DRV8353Rx-EVM電路圖（1）：MD016A

圖17.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（1）

圖18.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（2）

圖19.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（3）

圖20.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（4）

圖21.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（5）

圖22.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（6）

圖23.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（7）

圖24.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（8）

圖25.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（9）

圖26.評(píng)估板DRV8353Rx-EVM MD016A PCB設(shè)計(jì)圖（10）

圖27.評(píng)估板DRV8353Rx-EVM MD016A（001）裝配圖

圖28.評(píng)估板DRV8353Rx-EVM MD016A（002）裝配圖

圖29.評(píng)估板DRV8353Rx-EVM MD017A電路圖（1）

圖30.評(píng)估板DRV8353Rx-EVM MD017A電路圖（2）

圖31.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（1）

圖32.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（2）

圖33.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（3）

圖34.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（4）

圖35.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（5）

圖36.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（6）

圖37.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（7）

圖38.評(píng)估板DRV8353Rx-EVM MD017A PCB設(shè)計(jì)圖（8）

圖39.評(píng)估板DRV8353Rx-EVM MD017A PCB裝配圖（1）

圖39.評(píng)估板DRV8353Rx-EVM MD017A PCB裝配圖（2）

評(píng)估板DRV8353Rx-EVM材料清單見(jiàn)：

MCU036A（001）_BOM.xls

MD016A（001）_BOM.xls

MD016A（002）_BOM.xls

slvc742a.zip

詳情請(qǐng)見(jiàn)：

和

drv8353.pdf