1.方案概述

此方案使用HD-8MMN-CORE的核心板搭配TI公司的芯片SN65DSI86轉(zhuǎn)換芯片實(shí)現(xiàn)。

SN65DSI86作為一款MIPI DSI轉(zhuǎn)eDP的芯片，支持雙通道DSI輸入，最大四通道顯示輸出，最大支持4K@60fps輸出，WUXGA 1080P。本方案中將采用單通道DSI輸入，雙通道DP輸出到1080p的屏幕。

HD8MMN-CORE系列工業(yè)級(jí)核心板基于NXP(Freescale) i.MX8MM系列Cortex-A53高性能處理器設(shè)計(jì)，支持硬件加密，支持?jǐn)z像頭接口、USB3.0接口、HDMI/MIPI、PCIe、千兆以太網(wǎng)接口、多路串口等，適用于快速開發(fā)一系列最具創(chuàng)新性的應(yīng)用，如多媒體應(yīng)用、人機(jī)界面、工業(yè)4.0、車載終端以及邊緣計(jì)算設(shè)備等。

2.硬件原理圖

注：硬件修改REFCLK上需要貼上27M的晶振，TEST2引腳需要通過(guò)4.7K電阻上拉到1.8V.

3.軟件實(shí)現(xiàn)

3.1軟件介紹

內(nèi)核版本：Linux5.10；

SN65DSI86驅(qū)動(dòng)：drivers/gpu/drm/bridge/ti-sn65dsi86.c

Panel驅(qū)動(dòng)：drivers/gpu/drm/panel/panel-simple.c

3.2驅(qū)動(dòng)移植

內(nèi)核配置，需要打開如下兩項(xiàng)

CONFIG_DRM_TI_SN65DSI86=y
CONFIG_DRM_PANEL_SIMPLE=y

1)設(shè)備樹配置

/ {
        osc_27m: clock-osc-27m {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <27000000>;
                clock-output-names = "osc_27m";
        };


        lcd_backlight: lcd_backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm1 0 100000>;
                status = "okay";


                brightness-levels = < 0  1  2  3  4  5  6  7  8  9
                                     10 11 12 13 14 15 16 17 18 19
                                     20 21 22 23 24 25 26 27 28 29
                                     30 31 32 33 34 35 36 37 38 39
                                     40 41 42 43 44 45 46 47 48 49
                                     50 51 52 53 54 55 56 57 58 59
                                     60 61 62 63 64 65 66 67 68 69
                                     70 71 72 73 74 75 76 77 78 79
                                     80 81 82 83 84 85 86 87 88 89
                                     90 91 92 93 94 95 96 97 98 99
                                    100>;
                enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
                default-brightness-level = <80>;
        };
        panel {
                compatible = "test,test-edp-1080p";        //設(shè)置自己的屏幕匹配參數(shù)組
                backlight = <&lcd_backlight>;
                no-hpd;


                port {
                        panel1_in: endpoint {
                                remote-endpoint = <&sn65_out>;
                        };
                };
        };
};
&pwm1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm1>;
        status = "okay";
};


&i2c4 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c4>;
        status = "okay";
        sn65dsi86@2d {
               …….
                clock-names = "refclk";          //默認(rèn)名字
          //SN65DSI86僅支持12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
                clocks = <&osc_27m>;


               ……
                        port@1 {
                                reg = <1>;
                                sn65_out: endpoint {
                                        //data-lanes = <0 1 2 3>;
                  //根據(jù)eDP屏的通道數(shù)設(shè)置，這里為2通道
                                        data-lanes = <0 1>; 
 ……

2)驅(qū)動(dòng)修改

添加顯示屏的顯示參數(shù)到驅(qū)動(dòng)中，修改drivers/gpu/drm/panel/panel-simple.c：

tatic const struct display_timing test_edp_1080p_timing = {
    .pixelclock = { 153000000, 153000000, 153000000 },
    .hactive = { 1920, 1920, 1920 },
    .hfront_porch = { 100, 100, 100 },
    …..
    .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
    .connector_type = DRM_MODE_CONNECTOR_eDP,  
};
static const struct of_device_id platform_of_match[] = {
    {
        .compatible = "test,test-edp-1080p",
        .data = &test_edp_1080p,
    },

修改sn65dsi86驅(qū)動(dòng)以適應(yīng)我們的板卡，修改drivers/gpu/drm/bridge/ti-sn65dsi86.c，修改DSI正確的模式，防止找不到注冊(cè)的panel出現(xiàn)報(bào)錯(cuò)“could not find any panel node”，開機(jī)過(guò)程中打印1次是正常的，SN65DSI86的驅(qū)動(dòng)找不到Panel會(huì)被多次調(diào)用，直到找到panel為止。

static int ti_sn_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
...     
//dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
    dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
             MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;

3)調(diào)試報(bào)錯(cuò)

在調(diào)試過(guò)程中碰到“Link training failed, link is off”的報(bào)錯(cuò)，是因?yàn)镾N65DSI86默認(rèn)只支持ASSR模式的eDP屏幕，對(duì)于不支持ASSR模式的eDP屏，硬件上則需要將TEST2引腳拉高到1.8V，且修改相關(guān)寄存器將芯片從ASSR模式變?yōu)橹С謽?biāo)準(zhǔn)的DP模式，修改如下：

#define SN_ENH_FRAME_REG            0x5A
#define ASSR_CONTROL              BIT(0)
...


static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx,
const char **last_err_str)  
{
    unsigned int val;
int ret;
int i;


/* set dp clk frequency value */
    regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
              DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));


    regmap_write(pdata->regmap, 0xff, 0x07);
    regmap_write(pdata->regmap, 0x16, 0x01);
    regmap_write(pdata->regmap, 0xff, 0x00);
/* For DisplayPort, use the standard DP scrambler seed. */
    regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,ASSR_CONTROL, 0);
/* enable DP PLL */
    regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
...

如果未接eDP屏幕會(huì)出現(xiàn)如下報(bào)錯(cuò)：

[2.299284]ti_sn65dsi86 3-002d:[drm:ti_sn_bridge_enable]ERROR Can't read lane count(-6);assuming 4
 [ 2.765851] ti_sn65dsi86 3-002d: [drm:ti_sn_bridge_enable] ERROR Can't read eDP rev (-6), assuming 1.1

審核編輯：劉清